2048 search results - page 18 / 410 » Optimizing pipelines for power and performance |
CODES
2001
IEEE
15 years 1 months ago
2001
IEEE
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
FCCM
2009
IEEE
15 years 4 months ago
2009
IEEE
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
72
Voted
SAC
2010
ACM
15 years 4 months ago
2010
ACM
In this paper we present an optimization solution for power and performance management in a platform running multiple independent applications. Our approach assumes a virtualized ...