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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
15 years 6 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 4 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
ICCAD
1998
IEEE
130views Hardware» more  ICCAD 1998»
15 years 4 months ago
GPCAD: a tool for CMOS op-amp synthesis
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be fo...
Maria del Mar Hershenson, Stephen P. Boyd, Thomas ...
DAC
2005
ACM
15 years 2 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
15 years 9 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou