867 search results - page 54 / 174 » Optimizing synthesis with metasketches |
98
Voted
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
15 years 4 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
RTCSA
1999
IEEE
15 years 4 months ago
1999
IEEE
Abstract. We present an approach to static priority preemptive process scheduling for the synthesis of hard realtime distributed embedded systems where communication plays an impor...
86
Voted
ICCAD
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. Entire subdesigns can efficie...
106
Voted
IEICET
2006
15 years 14 days ago
2006
Abstract--This paper deals with a synthesis of a nonautonomous system with a stable limit cycle. By extending Green's method, by which arbitrary periodic solutions can be desi...
81
Voted
DAC
2009
ACM
16 years 1 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...