1990 search results - page 109 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
144
Voted
ASPLOS
2004
ACM
15 years 9 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
186
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HIPEAC
2011
Springer
14 years 3 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
116
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Although a loosely coupled component-based framework offers flexibility and versatility for building and deploying large-scale multi-physics simulation systems, the performance o...
122
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VLDB
1999
ACM
15 years 8 months ago
1999
ACM
Data intensive applications today usually run in either a clientserver or a middleware environment. In either case, they must efficiently handle both database queries, which proc...
121
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...