1990 search results - page 206 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
139
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ISCA
1996
IEEE
15 years 9 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
155
Voted
ICCS
2009
Springer
15 years 11 months ago
2009
Springer
The development of optimized codes is time-consuming and requires extensive architecture, compiler, and language expertise, therefore, computational scientists are often forced to ...
167
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IPPS
2000
IEEE
15 years 8 months ago
2000
IEEE
Metacomputing infrastructures couple multiple clusters (or MPPs) via wide-area networks. A major problem in programming parallel applications for such platforms is their hierarchi...
134
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ISCA
2006
IEEE
15 years 11 months ago
2006
IEEE
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
171
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WOSP
2004
ACM
15 years 10 months ago
2004
ACM
The simulated evaluation of memory management policies relies on reference traces—logs of memory operations performed by running processes. No existing approach to reference tra...