1990 search results - page 228 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
149
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GI
2009
Springer
15 years 2 months ago
2009
Springer
: The performance potential of multistatic sonar operations has been investigated by several research institutes and proven in numerous international sea trials during the last yea...
190
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HPCA
2012
IEEE
14 years 15 days ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
166
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MICRO
2008
IEEE
15 years 11 months ago
2008
IEEE
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
136
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IPPS
2009
IEEE
15 years 11 months ago
2009
IEEE
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...
199
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AOSD
2005
ACM
15 years 10 months ago
2005
ACM
C applications, in particular those using operating system level services, frequently comprise multiple crosscutting concerns: network protocols and security are typical examples ...