1990 search results - page 43 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
110
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DAC
2000
ACM
16 years 2 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
MICRO
1999
IEEE
15 years 6 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
116
Voted
EUROPAR
2004
Springer
15 years 7 months ago
2004
Springer
Address correlation is a technique that links the addresses that reference the same data values. Using a detailed source-code level analysis, a recent study [1] revealed that diffe...
133
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
99
Voted
ICS
2009
Tsinghua U.
15 years 8 months ago
2009
Tsinghua U.
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...