1990 search results - page 85 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
125
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CLUSTER
2007
IEEE
15 years 8 months ago
2007
IEEE
Bulk memory copies incur large overheads such as CPU stalling (i.e., no overlap of computation with memory copy operation), small register-size data movement, cache pollution, etc...
124
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ICCD
2007
IEEE
16 years 29 days ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
107
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OSDI
1996
ACM
15 years 5 months ago
1996
ACM
High-performance I/O systems depend on prefetching and caching in order to deliver good performance to applications. These two techniques have generally been considered in isolati...
135
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
151
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
Ever scaling process technology makes embedded systems more vulnerable to soft errors than in the past. One of the generic methods used to fight soft errors is based on duplicati...