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ERSA
2006
82views Hardware» more  ERSA 2006»
15 years 5 months ago
Cache Architectures for Reconfigurable Hardware
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...
Sebastian Lange, Martin Middendorf
IPPS
2007
IEEE
15 years 10 months ago
Optimizing Sorting with Machine Learning Algorithms
The growing complexity of modern processors has made the development of highly efficient code increasingly difficult. Manually developing highly efficient code is usually expen...
Xiaoming Li, María Jesús Garzar&aacu...
AINA
2003
IEEE
15 years 9 months ago
Incremental Updates on Mobile Datawarehousing Using Optimized Hierarchical Views and New Aggregation Operators
The use of mobile applications is increasing rapidly. Particularly, mobile applications for decision support systems, such as mobile datawarehouses, are very attractive. However, ...
Marcus Costa Sampaio, Plácido Marinho Dias,...
DSN
2009
IEEE
15 years 8 months ago
An efficient XOR-scheduling algorithm for erasure codes encoding
In large storage systems, it is crucial to protect data from loss due to failures. Erasure codes lay the foundation of this protection, enabling systems to reconstruct lost data w...
Jianqiang Luo, Lihao Xu, James S. Plank
MDM
2005
Springer
165views Communications» more  MDM 2005»
15 years 9 months ago
STEP: Self-Tuning Energy-safe Predictors
Data access prediction has been proposed as a mechanism to overcome latency lag, and more recently as a means of conserving energy in mobile systems. We present a fully adaptive p...
James Larkby-Lahet, Ganesh Santhanakrishnan, Ahmed...