1990 search results - page 94 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
117
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
139
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CGO
2007
IEEE
15 years 10 months ago
2007
IEEE
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...
146
Voted
IPPS
2010
IEEE
15 years 2 months ago
2010
IEEE
From the point of view of an operating system, a computer is managed and optimized in terms of the application programming model and the management of system resources. For the TF...
125
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ICCAD
1999
IEEE
15 years 8 months ago
1999
IEEE
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
116
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MICRO
2006
IEEE
15 years 10 months ago
2006
IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...