1990 search results - page 99 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
128
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MICRO
2005
IEEE
15 years 9 months ago
2005
IEEE
The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interp...
122
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CASES
2003
ACM
15 years 9 months ago
2003
ACM
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
153
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TC
2010
15 years 2 months ago
2010
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
143
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SC
2009
ACM
15 years 11 months ago
2009
ACM
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
133
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CODES
2005
IEEE
15 years 9 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...