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117
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PDPTA
2007
15 years 5 months ago
Suppressing Independent Loops in Packing/Unpacking Loop Nest to Reduce Message Size for Message-passing Code
- In this paper we experiment with two optimization techniques we are considering implementing in a parallelizing compiler that generates parallel code for a distributed-memory sys...
P. Jerry Martin, Clayton S. Ferner
147
Voted
IPPS
2007
IEEE
15 years 10 months ago
Analysis of a Computational Biology Simulation Technique on Emerging Processing Architectures
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
Jeremy S. Meredith, Sadaf R. Alam, Jeffrey S. Vett...
127
Voted
CCGRID
2009
IEEE
15 years 10 months ago
Performance under Failures of DAG-based Parallel Computing
— As the scale and complexity of parallel systems continue to grow, failures become more and more an inevitable fact for solving large-scale applications. In this research, we pr...
Hui Jin, Xian-He Sun, Ziming Zheng, Zhiling Lan, B...
151
Voted
ICPPW
2008
IEEE
15 years 10 months ago
Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
Xingfu Wu, Valerie E. Taylor, Charles W. Lively, S...
137
Voted
IPPS
2006
IEEE
15 years 9 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner