Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
—We propose novel discrete cosine transform (DCT) pseudophase techniques to estimate shift/delay between two onedimensional (1-D) signals directly from their DCT coefficients by...
Abstract. In data grid, large quantity of data files is produced and data replication is applied to reduce data access time. Efficiently utilizing grid resources becomes important ...
Sang-Min Park, Jai-Hoon Kim, Young-Bae Ko, Won-Sik...
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...