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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
12 years 12 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
12 years 12 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
CISIS
2010
IEEE
15 years 2 months ago
A Parallel Programming Framework for Multi-core DNA Sequence Alignment
—A new parallel programming framework for DNA sequence alignment in homogeneous multi-core processor architectures is proposed. Contrasting with traditional coarse-grained parall...
Tiago Jose Barreiros Martins de Almeida, Nuno Fili...
VLDB
2007
ACM
204views Database» more  VLDB 2007»
15 years 3 months ago
Optimization of Frequent Itemset Mining on Multiple-Core Processor
Multi-core processors are proliferated across different domains in recent years. In this paper, we study the performance of frequent pattern mining on a modern multi-core machine....
Eric Li, Li Liu
ANCS
2009
ACM
14 years 7 months ago
An adaptive hash-based multilayer scheduler for L7-filter on a highly threaded hierarchical multi-core server
Ubiquitous multi-core-based web servers and edge routers are increasingly popular in deploying computationally intensive Deep Packet Inspection (DPI) programs. Previous work has s...
Danhua Guo, Guangdeng Liao, Laxmi N. Bhuyan, Bin L...