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» Packet Reordering in Network Processors
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DATE
2007
IEEE
133views Hardware» more  DATE 2007»
15 years 4 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...
ICC
2007
IEEE
166views Communications» more  ICC 2007»
15 years 4 months ago
Accuracy and Dynamics of Multi-Stage Load Balancing for Multipath Internet Routing
— Flow-based load balancing algorithms for multipath Internet routing are often used for traffic engineering. However, the target load distribution and the load balanced result ...
Rüdiger Martin, Michael Menth, Michael Hemmke...
ANCS
2006
ACM
15 years 3 months ago
Design of a web switch in a reconfigurable platform
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In...
Christoforos Kachris, Stamatis Vassiliadis
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 3 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
ANCS
2008
ACM
14 years 11 months ago
A remotely accessible network processor-based router for network experimentation
Over the last decade, programmable Network Processors (NPs) have become widely used in Internet routers and other network components. NPs enable rapid development of complex packe...
Charlie Wiseman, Jonathan S. Turner, Michela Becch...