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ISPA
2007
Springer
15 years 11 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ISCAS
2006
IEEE
163views Hardware» more  ISCAS 2006»
15 years 11 months ago
ASIC hardware implementation of the IDEA NXT encryption algorithm
— Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a nov...
Marco Macchetti, Wenyu Chen
WOWMOM
2006
ACM
91views Multimedia» more  WOWMOM 2006»
15 years 11 months ago
A Station-Based Adaptation Algorithm to Improve Robustness of IEEE 802.11
This paper studies a Bad Apple phenomenon caused by Head-of-Line blocking in IEEE 802.11 networks. This problem can adversely affect the performance of wireless multimedia streami...
Jean Cao, Yujing Wu, Carey L. Williamson
144
Voted
PAKDD
2005
ACM
161views Data Mining» more  PAKDD 2005»
15 years 11 months ago
Online Algorithms for Mining Inter-stream Associations from Large Sensor Networks
We study the problem of mining frequent value sets from a large sensor network. We discuss how sensor stream data could be represented that facilitates efficient online mining and ...
K. K. Loo, Ivy Tong, Ben Kao
CHES
2003
Springer
247views Cryptology» more  CHES 2003»
15 years 10 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
Pawel Chodowiec, Kris Gaj