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CGO
2006
IEEE
15 years 6 months ago
Compiling for EDGE Architectures
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
Aaron Smith, Jon Gibson, Bertrand A. Maher, Nichol...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 6 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
INFOCOM
2006
IEEE
15 years 6 months ago
Cross-Layer Congestion Control, Routing and Scheduling Design in Ad Hoc Wireless Networks
Abstract— This paper considers jointly optimal design of crosslayer congestion control, routing and scheduling for ad hoc wireless networks. We first formulate the rate constrai...
Lijun Chen, Steven H. Low, Mung Chiang, John C. Do...
103
Voted
ICPADS
2005
IEEE
15 years 6 months ago
A Two-Level Strategy for Topology Control in Wireless Sensor Networks
— This paper presents a two-level strategy for topology control in wireless sensor networks. The energy saving methods in most of the existing research work can be categorized in...
Bolian Yin, Hongchi Shi, Yi Shang
97
Voted
PLDI
2005
ACM
15 years 6 months ago
Demystifying on-the-fly spill code
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
Alex Aletà, Josep M. Codina, Antonio Gonz&a...
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