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ISPA
2007
Springer
15 years 3 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ISORC
2000
IEEE
15 years 1 months ago
Experimentation in CPU Control with Real-Time Java
This paper describes experiences in using an O.O. language (Java) in designing, prototyping and evaluating a CPU manager. QoS Animator facilitates the execution of object oriented...
Gerasimos Xydas, Jerome Tassel
CF
2007
ACM
15 years 1 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
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GECCO
2007
Springer
201views Optimization» more  GECCO 2007»
15 years 3 months ago
A parallel framework for loopy belief propagation
There are many innovative proposals introduced in the literature under the evolutionary computation field, from which estimation of distribution algorithms (EDAs) is one of them....
Alexander Mendiburu, Roberto Santana, Jose Antonio...
IEEEPACT
2003
IEEE
15 years 2 months ago
Design Trade-Offs in High-Throughput Coherence Controllers
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
Anthony-Trung Nguyen, Josep Torrellas