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ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
15 years 4 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
IJCNN
2007
IEEE
15 years 4 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...
IPPS
2007
IEEE
15 years 4 months ago
Integrated Environment for Embedded Control Systems Design
The motivation of our work is to make a design tool for distributed embedded systems compliant with HIS and AUTOSAR. The tool is based on Processor Expert, a component oriented de...
Roman Bartosinski, Zdenek Hanzálek, Petr St...
IPPS
2006
IEEE
15 years 3 months ago
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framew
In reconfigurable systems, reconfiguration latency is a very important factor impact the system performance. In this paper, a framework is proposed that integrates the temporal pa...
Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahma...
ISCAS
2006
IEEE
205views Hardware» more  ISCAS 2006»
15 years 3 months ago
A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters
A novel 0. 13,um CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC ml architecture uses current starved inverters where the inverter delay ver...
Holly Pekau, A. Yousif, James W. Haslett