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IPPS
2009
IEEE
15 years 11 months ago
Flexible pipelining design for recursive variable expansion
Many image and signal processing kernels can be optimized for performance consuming a reasonable area by doing loops parallelization with extensive use of pipelining. This paper p...
Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor ...
IPPS
2008
IEEE
15 years 11 months ago
Online scheduling in grids
This paper addresses nonclairvoyant and nonpreemptive online job scheduling in Grids. In the applied basic model, the Grid system consists of a large number of identical processor...
Uwe Schwiegelshohn, Andrei Tchernykh, Ramin Yahyap...
IPPS
2007
IEEE
15 years 11 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
SIPS
2007
IEEE
15 years 11 months ago
Sphere Decoding for Multiprocessor Architectures
Motivated by the need for high throughput sphere decoding for multipleinput-multiple-output (MIMO) communication systems, we propose a parallel depth-first sphere decoding (PDSD)...
Qi Qi, Chaitali Chakrabarti
ARITH
2005
IEEE
15 years 10 months ago
Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters
Saturating counters are a newly defined class of generalized parallel counters that provide the exact number of inputs which are equal to 1 only if this number is below a given t...
Zhaojun Wo, Israel Koren