5553 search results - page 156 / 1111 » Parallel Implementation of Sch |
131
Voted
HPCA
2009
IEEE
16 years 3 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
134
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EUROPAR
2004
Springer
15 years 8 months ago
2004
Springer
The BlueGene/L supercomputer will consist of 65,536 dual-processor compute nodes interconnected by two high-speed networks: a three-dimensional torus network and a tree topology ne...
161
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FIDJI
2003
Springer
15 years 8 months ago
2003
Springer
The popular slogan ”write once, run anywhere” effectively renders the expressive capabilities of the Java programming framework for developing, deploying, and reusing target-i...
158
Voted
RIDE
1996
IEEE
15 years 7 months ago
1996
IEEE
METU INteroperable DBMS (MIND) is a multidatabase system based on OMG's distributed object management architecture. It is implemented on top of a CORBA compliant ORB, namely,...
172
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DELTA
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...