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EUROPAR
2009
Springer
16 years 20 days ago
Parallel Lattice Basis Reduction Using a Multi-threaded Schnorr-Euchner LLL Algorithm
Abstract. In this paper, we introduce a new parallel variant of the LLL lattice basis reduction algorithm. Our new, multi-threaded algorithm is the first to provide an efficient,...
Werner Backes, Susanne Wetzel
150
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IPPS
2007
IEEE
16 years 12 days ago
Challenges in Mapping Graph Exploration Algorithms on Advanced Multi-core Processors
Multi-core processors are a shift of paradigm in computer architecture that promises a dramatic increase in performance. But multi-core processors also bring an unprecedented leve...
Oreste Villa, Daniele Paolo Scarpazza, Fabrizio Pe...
CASES
2007
ACM
15 years 10 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
ICWS
2010
IEEE
15 years 7 months ago
Highly Scalable Web Service Composition Using Binary Tree-Based Parallelization
Data intensive applications, e.g. in life sciences, pose new efficiency challenges to the service composition problem. Since today computing power is mainly increased by multiplica...
Patrick Hennig, Wolf-Tilo Balke
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
16 years 15 days ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li