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ICPP
2008
IEEE
15 years 9 months ago
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...
Sangyeun Cho, Socrates Demetriades, Shayne Evans, ...
IEEEPACT
2000
IEEE
15 years 7 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
PDP
2010
IEEE
15 years 8 months ago
Load Balancing Algorithms with Partial Information Management for the DLML Library
Abstract—Load balancing algorithms are an essential component of parallel computing reducing the response time of applications. Frequently, balancing algorithms have a centralize...
Juan Santana-Santana, Miguel A. Castro-Garcí...
CCGRID
2010
IEEE
15 years 4 months ago
High Performance Dimension Reduction and Visualization for Large High-Dimensional Data Analysis
Abstract--Large high dimension datasets are of growing importance in many fields and it is important to be able to visualize them for understanding the results of data mining appro...
Jong Youl Choi, Seung-Hee Bae, Xiaohong Qiu, Geoff...
IPPS
2007
IEEE
15 years 9 months ago
Experience of Optimizing FFT on Intel Architectures
Automatic library generators, such as ATLAS [11], Spiral [8] and FFTW [2], are promising technologies to generate efficient code for different computer architectures. The library...
Daniel Orozco, Liping Xue, Murat Bolat, Xiaoming L...