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HOTI
2008
IEEE
15 years 9 months ago
QsNetIII an Adaptively Routed Network for High Performance Computing
—In this paper we describe QsNetIII , an adaptively routed network for High Performance Computing (HPC) applications. We detail the structure of the network, the evolution of our...
Duncan Roweth, Trevor Jones
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
15 years 9 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson
HPCA
2007
IEEE
15 years 9 months ago
Optical Interconnect Opportunities for Future Server Memory Systems
This paper deals with alternative server memory architecture options in multicore CPU generations using optically-attached memory systems. Thanks to its large bandwidth-distance p...
Y. Katayama, A. Okazaki
IPPS
2007
IEEE
15 years 9 months ago
Modeling Modern Micro-architectures using CASL
We overview CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast prototyping and tool ...
Edward K. Walters II, J. Eliot B. Moss, Trek S. Pa...
IPPS
2007
IEEE
15 years 9 months ago
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks
DSP applications can be suitably represented using Process Network Models. This paper uses a modification of Kahn Process Network to solve the problem of finding an optimum arch...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker