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ICASSP
2008
IEEE
15 years 4 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
SCHOLARPEDIA
2011
14 years 16 days ago
N-body simulations
Abstract. Scientists’ ability to generate and collect massive-scale datasets is increasing. As a result, constraints in data analysis capability rather than limitations in the av...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
15 years 4 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
INFOCOM
2012
IEEE
13 years 5 days ago
Block permutations in Boolean Space to minimize TCAM for packet classification
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
Rihua Wei, Yang Xu, H. Jonathan Chao
CLUSTER
2008
IEEE
15 years 4 months ago
Towards an understanding of the performance of MPI-IO in Lustre file systems
—Lustre is becoming an increasingly important file system for large-scale computing clusters. The problem, however, is that many data-intensive applications use MPI-IO for their ...
Jeremy Logan, Phillip M. Dickens