1075 search results - page 74 / 215 » Parallel Programming with Transactional Memory |
109
Voted
CAV
2010
Springer
15 years 6 months ago
2010
Springer
Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a chal...
129
Voted
EUROPAR
2008
Springer
15 years 4 months ago
2008
Springer
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
173
Voted
ICLP
2011
Springer
14 years 6 months ago
2011
Springer
Transaction Logic is an extension of classical logic that gracefully integrates both declarative and procedural knowledge and has proved itself as a powerful formalism for many ad...
127
Voted
IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
127
Voted
HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...