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HPCA
2009
IEEE
16 years 5 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
HPCA
2009
IEEE
16 years 5 months ago
Variation-aware dynamic voltage/frequency scaling
Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. Although manufacturing pr...
Sebastian Herbert, Diana Marculescu
HPCA
2009
IEEE
16 years 5 months ago
Lightweight predication support for out of order processors
The benefits of Out of Order (OOO) processing are well known, as is the effectiveness of predicated execution for unpredictable control flow. However, as previous research has dem...
Mark Stephenson, Lixin Zhang, Ram Rangan
HPCA
2009
IEEE
16 years 5 months ago
Voltage emergency prediction: Using signatures to reduce operating margins
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations i...
Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. H...
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HPCA
2009
IEEE
16 years 5 months ago
Feedback mechanisms for improving probabilistic memory prefetching
This paper presents three techniques for improving the effectiveness of the recently proposed Adaptive Stream Detection (ASD) prefetching mechanism. The ASD prefetcher is a standa...
Ibrahim Hur, Calvin Lin
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