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CF
2010
ACM
15 years 4 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
210
Voted
ICDE
2007
IEEE
182views Database» more  ICDE 2007»
16 years 1 months ago
DIKNN: An Itinerary-based KNN Query Processing Algorithm for Mobile Sensor Networks
Current approaches to K Nearest Neighbor (KNN) search in mobile sensor networks require certain kind of indexing support. This index could be either a centralized spatial index or...
Shan-Hung Wu, Kun-Ta Chuang, Chung-Min Chen, Ming-...
HPCA
2009
IEEE
16 years 6 days ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
HPCA
2008
IEEE
16 years 1 days ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
114
Voted
HPCA
2007
IEEE
16 years 1 days ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...