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IPPS
2007
IEEE
15 years 8 months ago
Optimization and evaluation of parallel I/O in BIPS3D parallel irregular application
This paper presents the optimization and evaluation of parallel I/O for the BIPS3D parallel irregular application, a 3-dimensional simulation of BJT and HBT bipolar devices. The p...
Rosa Filgueira, David E. Singh, Florin Isaila, Jes...
IEEEPACT
1997
IEEE
15 years 6 months ago
A Parallel Algorithm for Compile-Time Scheduling of Parallel Programs on Multiprocessors
† In this paper, we propose a parallel randomized algorithm, called Parallel Fast Assignment using Search Technique (PFAST), for scheduling parallel programs represented by direc...
Yu-Kwong Kwok, Ishfaq Ahmad
105
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HPCA
1999
IEEE
15 years 6 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
IPPS
1994
IEEE
15 years 6 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ICDCS
2012
IEEE
13 years 4 months ago
DARD: Distributed Adaptive Routing for Datacenter Networks
Datacenter networks typically have many paths connecting each host pair to achieve high bisection bandwidth for arbitrary communication patterns. Fully utilizing the bisection ban...
Xin Wu, Xiaowei Yang