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» Parallel buffers for chip multiprocessors
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PDP
2009
IEEE
15 years 4 months ago
Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
Avneesh Pant, Hassan Jafri, Volodymyr V. Kindraten...
DSD
2006
IEEE
83views Hardware» more  DSD 2006»
15 years 1 months ago
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
Abstract. Network-on-chip-based multiprocessor systems-onchip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel p...
Sander Stuijk, Twan Basten, Marc Geilen, Amir Hoss...
TPDS
2010
260views more  TPDS 2010»
14 years 8 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear
73
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EUROPAR
1997
Springer
15 years 1 months ago
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...
Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, K...
ICPADS
2006
IEEE
15 years 3 months ago
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Tayl...