284 search results - page 15 / 57 » Parallel buffers for chip multiprocessors |
80
Voted
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
Power management is critical in server and high-performancecomputing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support ...
80
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
58
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must explo...
HPCC
2009
Springer
15 years 2 months ago
2009
Springer
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...