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» Parallel buffers for chip multiprocessors
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HIPC
2004
Springer
15 years 3 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
CAL
2006
14 years 9 months ago
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
James Donald, Margaret Martonosi
ICPPW
2008
IEEE
15 years 4 months ago
Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
Xingfu Wu, Valerie E. Taylor, Charles W. Lively, S...
IPPS
2007
IEEE
15 years 4 months ago
A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
Richard T. Saunders, Clinton L. Jeffery, Derek T. ...
ICDM
2006
IEEE
147views Data Mining» more  ICDM 2006»
15 years 3 months ago
Adaptive Parallel Graph Mining for CMP Architectures
Mining graph data is an increasingly popular challenge, which has practical applications in many areas, including molecular substructure discovery, web link analysis, fraud detect...
Gregory Buehrer, Srinivasan Parthasarathy, Yen-Kua...