284 search results - page 36 / 57 » Parallel buffers for chip multiprocessors |
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
We present Program Demultiplexing (PD), an execution paradigm that creates concurrency in sequential programs by "demultiplexing" methods (functions or subroutines). Cal...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
ICS
2000
Tsinghua U.
15 years 1 months ago
2000
Tsinghua U.
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
74
Voted
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
Clusters of Symmetric MultiProcessing (SMP) nodes with multi-core Chip-Multiprocessors (CMP), also known as SMP-CMP clusters, are becoming ubiquitous today. For Message Passing int...
SBCCI
2005
ACM
15 years 3 months ago
2005
ACM
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...