284 search results - page 45 / 57 » Parallel buffers for chip multiprocessors |
90
Voted
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
CGO
2008
IEEE
15 years 4 months ago
2008
IEEE
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
108
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CF
2010
ACM
15 years 2 months ago
2010
ACM
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
208
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ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
98
Voted
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...