284 search results - page 53 / 57 » Parallel buffers for chip multiprocessors |
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
ICS
1999
Tsinghua U.
15 years 1 months ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
In today’s dynamic computing environments, the available resources and even underlying computation engine can change during the execution of a program. Additionally, current tre...
70
Voted
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...