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» Parallel buffers for chip multiprocessors

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ISCA
2007
IEEE

161views Hardware» more ISCA 2007»

Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors

15 years 3 months ago

Download physbam.stanford.edu

We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and...

Christopher J. Hughes, Radek Grzeszczuk, Eftychios...

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ASAP
2005
IEEE

182views Hardware» more ASAP 2005»

A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor

15 years 3 months ago

Download vassilios-chouliaras.com

We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...

Tom R. Jacobs, José L. Núñez-...

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CJ
2006

84views more CJ 2006»

Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors

14 years 9 months ago

Download staff.science.uva.nl

Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...

Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope

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ISPASS
2005
IEEE

96views Software Engineering» more ISPASS 2005»

Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors

15 years 3 months ago

Download www.csl.cornell.edu

Jian Li, José F. Martínez

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