In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
K. Van Renterghem, P. Demuytere, Dieter Verhulst, ...
In this paper we present a solution for efficient porting of sequential C++ applications on the Cell B.E. processor. We present our step-by-step approach, focusing on its general...
Ana Lucia Varbanescu, Henk J. Sips, Kenneth A. Ros...
Earlier work has developed the underpinnings of IC-Scheduling Theory, an algorithmic framework for scheduling computations having intertask dependencies for Internet-based computi...
Gennaro Cordasco, Grzegorz Malewicz, Arnold L. Ros...
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
In distributed hybrid computing systems, traditional sequential processors are loosely coupled with reconfigurable hardware for optimal performance. This loose coupling proves to...