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» Parallel error correcting codes
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124
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CORR
2008
Springer
137views Education» more  CORR 2008»
15 years 2 months ago
Counteracting Byzantine Adversaries with Network Coding: An Overhead Analysis
Network coding increases throughput and is robust against failures and erasures. However, since it allows mixing of information within the network, a single corrupted packet genera...
MinJi Kim, Muriel Médard, João Barro...
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
15 years 9 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
MICRO
2010
IEEE
186views Hardware» more  MICRO 2010»
15 years 11 days ago
SAFER: Stuck-At-Fault Error Recovery for Memories
As technology scaling poses a threat to DRAM scaling due to physical limitations such as limited charge, alternative memory technologies including several emerging non-volatile me...
Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Sriniv...
132
Voted
TOOLS
2009
IEEE
15 years 9 months ago
Guaranteeing Syntactic Correctness for All Product Line Variants: A Language-Independent Approach
A software product line (SPL) is a family of related program variants in a well-defined domain, generated from a set of features. A fundamental difference from classical applicati...
Christian Kästner, Sven Apel, Salvador Trujil...
TIT
2010
107views Education» more  TIT 2010»
14 years 9 months ago
On the efficiency of shortened cyclic single-burst-correcting codes
Shortened cyclic codes that are capable of correcting up to a single burst of errors are considered. The efficiency of such codes has been analized by how well they approximate the...
Luis Javier García-Villalba, José Re...