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» Parallel placement for field-programmable gate arrays
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IPPS
2007
IEEE
15 years 4 months ago
Miss Ratio Improvement For Real-Time Applications Using Fragmentation-Aware Placement
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
Ahmed Abou ElFarag, Hatem M. El-Boghdadi, Samir I....
IPPS
2006
IEEE
15 years 3 months ago
Securing embedded programmable gate arrays in secure circuits
The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing ...
Nicolas Valette, Lionel Torres, Gilles Sassatelli,...
IPPS
2006
IEEE
15 years 3 months ago
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Ch...
Michael Hübner, Christian Schuck, Jürgen...
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 7 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ERSA
2009
149views Hardware» more  ERSA 2009»
14 years 7 months ago
Harnessing Human Computation Cycles for the FPGA Placement Problem
Harnessing human computation is an approach to find problem solutions. In this paper, we investigate harnessing this human computation for a Field Programmable Gate Array (FPGA) p...
Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit S...