104 search results - page 13 / 21 » Parallel processor scheduling with delay constraints |
IPPS
2008
IEEE
15 years 6 months ago
2008
IEEE
High-performance microprocessors, e.g., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational require...
104
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ASPLOS
1992
ACM
15 years 3 months ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
SBACPAD
2007
IEEE
15 years 5 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
100
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LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
103
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ICALP
2010
Springer
15 years 1 months ago
2010
Springer
We present a new deterministic sorting algorithm that interleaves the partitioning of a sample sort with merging. Sequentially, it sorts n elements in O(n log n) time cache-oblivi...