770 search results - page 114 / 154 » Parallel simulation of chip-multiprocessor architectures |
116
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ISSS
1998
IEEE
15 years 6 months ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
115
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ISCA
2011
IEEE
14 years 5 months ago
2011
IEEE
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
99
Voted
JSSPP
2004
Springer
15 years 7 months ago
2004
Springer
Using a single traditional gang scheduling algorithm cannot provide the best performance for all workloads and parallel architectures. A solution for this problem is the use of...
111
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IPPS
2000
IEEE
15 years 6 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
108
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PODC
1994
ACM
15 years 6 months ago
1994
ACM
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...