770 search results - page 49 / 154 » Parallel simulation of chip-multiprocessor architectures |
126
Voted
ICCD
1997
IEEE
15 years 6 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
130
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PARLE
1992
15 years 6 months ago
1992
Complex and data-intensive database queries mandate parallel processing strategies to achieve sufficiently short response times. In praxis, parallel database processing is mostly b...
115
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ISCA
2010
IEEE
15 years 6 months ago
2010
IEEE
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
104
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ROBIO
2006
IEEE
15 years 8 months ago
2006
IEEE
— The architecture optimization of a three degrees of freedom (3-DOF) planar cable-driven parallel manipulator (CDPM) with multiple objectives has been implemented by means of GA...
125
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PPOPP
2006
ACM
15 years 7 months ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...