770 search results - page 54 / 154 » Parallel simulation of chip-multiprocessor architectures |
ICCD
2006
IEEE
15 years 11 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
120
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GECCO
2007
Springer
15 years 8 months ago
2007
Springer
Engineering design increasingly uses computer simulation models coupled with optimization algorithms to find the best design that meets the customer constraints within a time con...
124
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HPDC
1997
IEEE
15 years 6 months ago
1997
IEEE
This paper presents a novel networking architecture designed for communication intensive parallel applications running on clusters of workstations (COWs) connected by highspeed ne...
PPOPP
2003
ACM
15 years 7 months ago
2003
ACM
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able t...
133
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PPOPP
2006
ACM
15 years 8 months ago
2006
ACM
Large-scale simulations and computational modeling using molecular dynamics (MD) continues to make significant impacts in the field of biology. It is well known that simulations...