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IPPS
2005
IEEE
15 years 9 months ago
Fast Address Translation Techniques for Distributed Shared Memory Compilers
The Distributed Shared Memory (DSM) model is designed to leverage the ease of programming of the shared memory paradigm, while enabling the highperformance by expressing locality ...
François Cantonnet, Tarek A. El-Ghazawi, Pa...
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 9 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ICS
2005
Tsinghua U.
15 years 8 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
15 years 8 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
MOZ
2004
Springer
15 years 8 months ago
Compositional Abstractions for Search Factories
ional Abstractions for Search Factories Guido Tack, Didier Le Botlan MOZ 2004 Presented at International Mozart/Oz Conference (MOZ 2004) Charleroi, Belgium October 2004 Published i...
Guido Tack, Didier Le Botlan
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