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PPOPP
2010
ACM
16 years 2 months ago
Load balancing on speed
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
Steven Hofmeyr, Costin Iancu, Filip Blagojevic
HPCN
2000
Springer
15 years 11 months ago
An Analytical Model for a Class of Architectures under Master-Slave Paradigm
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
Yasemin Yalçinkaya, Trond Steihaug
IPPS
2009
IEEE
16 years 2 months ago
Flexible pipelining design for recursive variable expansion
Many image and signal processing kernels can be optimized for performance consuming a reasonable area by doing loops parallelization with extensive use of pipelining. This paper p...
Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor ...
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
16 years 1 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...
HPDC
2007
IEEE
16 years 1 months ago
Smartsockets: solving the connectivity problems in grid computing
Tightly coupled parallel applications are increasingly run in Grid environments. Unfortunately, on many Grid sites the ability of machines to create or accept network connections ...
Jason Maassen, Henri E. Bal