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ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
16 years 19 days ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
16 years 6 days ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
SOFTVIS
2003
ACM
15 years 11 months ago
Interactive Locality Optimization on NUMA Architectures
Optimizing the performance of shared-memory NUMA programs remains something of a black art, requiring that application writers possess deep understanding of their programs’ beha...
Tao Mu, Jie Tao, Martin Schulz, Sally A. McKee
ICALP
2010
Springer
15 years 11 months ago
Optimal Zielonka-Type Construction of Deterministic Asynchronous Automata
Abstract. Asynchronous automata are parallel compositions of finitestate processes synchronizing over shared variables. A deep theorem due to Zielonka says that every regular trac...
Blaise Genest, Hugo Gimbert, Anca Muscholl, Igor W...
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 10 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg