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ICASSP
2008
IEEE
15 years 9 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
PDP
2008
IEEE
15 years 9 months ago
Out-of-Core Wavefront Computations with Reduced Synchronization
Matrix computation algorithms often exhibit dependencies between neighboring elements inside loop nests such that the frontier between computed elements and those to be computed w...
Pierre-Nicolas Clauss, Jens Gustedt, Fréd&e...
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IPPS
2007
IEEE
15 years 9 months ago
Advanced Shortest Paths Algorithms on a Massively-Multithreaded Architecture
We present a study of multithreaded implementations of Thorup’s algorithm for solving the Single Source Shortest Path (SSSP) problem for undirected graphs. Our implementations l...
Joseph R. Crobak, Jonathan W. Berry, Kamesh Maddur...
HPCC
2007
Springer
15 years 9 months ago
Online Algorithms for Single Machine Schedulers to Support Advance Reservations from Grid Jobs
Advance Reservations(AR) make it possible to guarantee the QoS of Grid applications by reserving a particular resource capability over a defined time interval on local resources. H...
Bo Li, Dongfeng Zhao
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
15 years 9 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...