2 search results - page 1 / 1 » Pareto Points in SRAM Design Using the Sleepy Stack Approach |
69
Voted
VLSI
2005
Springer
15 years 2 months ago
2005
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
131
Voted
TC
2011
14 years 4 months ago
2011
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...