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» Partitioning of VLSI Circuits and Systems
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VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
15 years 10 months ago
Architecture and Design of a High Performance SRAM for SOC Design
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka P...
75
Voted
GLVLSI
1998
IEEE
169views VLSI» more  GLVLSI 1998»
15 years 1 months ago
On the Characterization of Multi-Point Nets in Electronic Designs
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those prop...
Dirk Stroobandt, Fadi J. Kurdahi
FCCM
2005
IEEE
151views VLSI» more  FCCM 2005»
15 years 3 months ago
Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems
In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
DFT
2008
IEEE
89views VLSI» more  DFT 2008»
15 years 4 months ago
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
Tolerating defects and fabrication variations will be critical in any system made with devices that have nanometer feature sizes. This paper considers how fabrication variations a...
Michael T. Niemier, Michael Crocker, Xiaobo Sharon...
GLVLSI
1999
IEEE
88views VLSI» more  GLVLSI 1999»
15 years 2 months ago
Logic in Wire: Using Quantum Dots to Implement a Microprocessor
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to loo...
Michael T. Niemier, Peter M. Kogge