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ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 2 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett
GLVLSI
2005
IEEE
144views VLSI» more  GLVLSI 2005»
15 years 3 months ago
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
Mikhail Popovich, Eby G. Friedman, Michael Sotman,...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
ISCAS
1999
IEEE
105views Hardware» more  ISCAS 1999»
15 years 2 months ago
Configuration self-test in FPGA-based reconfigurable systems
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for...
W. Quddus, Abhijit Jas, Nur A. Touba